This invention relates generally to techniques for the packaging of multiple circuit elements, and more particularly to structures for the interconnection of multiple circuit elements, such as circuit boards and integrated-circuit (IC) ("chip") packages. Complex circuitry is often implemented in the form of a number of multi-layer printed circuit boards, which must be appropriately interconnected to permit the circuitry to perform its intended function.
In the past, circuit boards in very large scale integration (VLSI) systems have been interconnected by means of "mother" boards having connectors into which the other circuit boards are plugged. An alternative approach uses cable harnesses and connectors to attach to the boards. The use of either mother boards or cable harnesses adds considerably to the cost of the finished product, and has another important consequence. For high-speed circuits in VLSI systems, a major concern is that interconnecting cables contribute a large amount of capacitance and inductance, and thereby limit the speed of operation of the circuitry. Insulation material that has to be used in the cable harness further increases interconnection reactances and aggravates this problem. Moreover, the use of cable harnesses can add as much as twenty-five percent to the volume of the entire assembly, and can add accordingly to the assembly weight.
Another significant problem arising from the use of cables and mother boards is that all input and output leads in each board must be terminated at an edge of the board, for attachment to a back-plane connector. A signal originating at an area of the board remote from the edge connector must weave its way through other conductors and components on the board. This necessitates long lead lengths and complicates the board design, often requiring additional board layers and a higher density of wiring.
In accordance with conventional packaging techniques, integrated-circuit chips are interconnected by means of multilayer printed circuit boards. The boards are, in turn, interconnected by a variety of "back-panel" wiring techniques using wire-wrap terminals, soldered terminals, and plug-in connectors.
Planar multilayer printed circuit boards include such materials as epoxy glass, Polymide, or ceramic materials, like aluminum oxide (Al.sub.2 O.sub.3). All of these materials have relatively high dielectric constants and present serious problems to the high-speed circuit designer. The distributed capacitance of the necessary interconnections in a high speed system using multilayer circuit boards may be so high as to demand a charging current that is a significant factor contributing to the total power dissipated in the circuitry. A related problem is that the distributed capacitance of the interconnections effectively limits their length if the capacitance values are to be kept within reasonable limits. For typical high speed systems, the associated printed circuit boards may have geometric features with widths of approximately 0.07 inches and spacings of the same dimension. For these parameters the associated distributed capacitance limits the maximum lead length to about 10 to 15 inches.
The reactances resulting from the use of conventional interconnection technology result in an even more important problem. High signal propagation times resulting from the interconnection reactances may render high speed system completely inoperative, or at best extremely limited in operating speed and data throughput.
The problems described with respect to high speed circuits have become aggravated in recent years as the complexity of the circuitry has increased. Also the chip packages themselves require very large numbers of leads for input and output of signals. Existing high speed circuit designs require up to two hundred input-output leads, and future designs could easily extend this requirement to around five hundred leads. To accommodate a modest chip package having 132 leads requires a circuit board with over sixteen layers. Moreover, some manufacturers are already using boards with up to thirty-three layers. Circuit boards of this complexity require considerable time to design and produce. A design change of even the simplest nature can result in scrapping of the associated circuit boards, at further cost to the manufacturer.
To obviate or minimize these problems that arise from the use of conventional interconnection techniques, it has become apparent that a new packaging approach must be employed. The new approach should minimize the lead lengths between interconnected circuits, and provide a correspondingly high packing density that makes more effective use of modern integrated-circuit fabrication techniques. The present invention is directed to these ends.